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1 SL2100 single chip synthesised broadband converter datasheet features single chip synthesised broadband solution compatible with both up converter and downconverter requirements in double conversion tuner applications compatible with digital and analogue system requirements cso < -62 dbc, ctb < -64 dbc extremely low phase noise balanced local oscillator, with i 2 c bus controlled band switching and with very low fundamental and harmonic radiation integral fast mode compliant i 2 c bus controlled pll frequency synthesiser designed for high comparison frequencies and low phase noise performance buffered crystal output for pipelining system reference frequency full esd protection. (normal esd handling procedures should be observed) applications double conversion tuners digital terrestrial tuners cable modems data transmit systems data communications systems ?atv description the SL2100 is a fully integrated single chip broadband mixer oscillator with on-board low phase ds5365 issue 1.2 november 2001 ordering information SL2100b/kg/np2s (tubes) SL2100b/kg/np2t (tape and reel) noise i 2 c bus controlled pll frequency synthesiser. it is intended primarily for application in double conversion tuners as both the up and down converter and is compatible with hiif frequencies up to 1.4 ghz and all standard tuner if output frequencies. the device contains all elements necessary, with the exception of local oscillator tuning network, loop ?ter and crystal reference to fabricate a complete synthesised block converter, compatible with digital and analogue requirements. figure 1 - pin allocation 28 SL2100 sda scl vcc vee vee vcc vee xtal cap xtal bufref rfinput rfinputb ifoutputb vee ifoutput vee vcc lo lob vcc vee add vee port p0 drive pump vee vcc np28
datasheet SL2100 2 quick reference data all data applies with the following conditions unless otherwise stated; a) nominal loads as follows; 1220 mhz output load as in ?ure (3) 44 mhz output load as in ?ure (4) b) input signal per carrier of 62 dbuv ?dbm assumes a 75 ? characteristic impedance, and 0 dbm = 109 dbuv characteristic units rf input operating range 50 - 1400 mhz input noise ?ure, ssb, 50-860 mhz 6.5 - 8.5 db 860 - 1400 8.5 - 12 db conversion gain 12 db ctb (fully loaded matrix) c -68 dbc cso (fully loaded matrix) c -65 dbc p1db input referred 110 dbuv local oscillator phase noise as upconverter ssb @ 10 khz offset c -90 dbc/hz ssb @ 100 khz offset c -112 dbc/hz local oscillator phase noise as downconverter ssb @ 10 khz offset c -93 dbc/hz ssb @ 100 khz offset c -115 dbc/hz local oscillator phase noise ?or -136 dbc/hz lo reradiation from rf input fundamental tbc dbuv second harmonic dbuv third harmonic dbuv pll spurs on converted output with input @ 60 dbuv c -70 dbc pll maximum comparison frequency 4 mhz pll phase noise at phase detector -152 dbc/hz
SL2100 datasheet 3 functional description the SL2100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board i 2 c bus controlled pll frequency synthesiser, optimised for application in double conversion tuner systems as both the up and down converter. it also has application in any system where a wide dynamic range broadband synthesised frequency converter is required. the SL2100 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. the pin assignment is contained in ?ure (1) and the block diagram in ?ure (2). converter section in normal application the rf input is interfaced through appropriate impedance matching and an agc front end to the device input. the rf input preampli?r of the device is designed for low noise ?ure, within the operating region of 50 to 1400 mhz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. the preampli?r also provides gain to the mixer section and back isolation from the local oscillator section. the typical rf input impedance and matching network for broadband upconversion are contained in ?ures (6) and (7) respectively and for narrow band downconversion in ?ures (8) and (9) respectively. the input referred two tone intermodulation test condition spectrum is shown in ?ure (10). the typical input nf is contained in ?ure (11) and the typical gain in ?ure (12). the output of the preampli?r is fed to the mixer section which is optimised for low radiation application. in this stage the rf signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. the oscillator block uses an external tuneable network and is optimised for low phase noise. the typical application as an upconverter is shown in ?ure (13) and the typical phase noise performance in ?ure (14). the typical application as a downconverter is shown in ?ure (15), and the phase noise performance in ?ure (17). this block interfaces direct with the internal pll to allow for frequency synthesis of the local oscillator. finally the output of the mixer provides an open collector differential output drive. the device allows for selection of an if in the range 30-1400 mhz so covering standard hiifs between 1 and 1.4 ghz and all conventional tuner output ifs. when used as a broadband upconverter to a hiif the output should be differentially loaded, for example with a differential saw ?ter, to maximise intermodulation performance. a nominal load is shown in ?ure (3), which will typically be terminated with a differential 200 ? load. when used as a narrowband downconverter the output should be differentially loaded, either with a discrete differential to single ended converter as in ?ure (4), shown tuned to 44 mhz if, or direct in to a differential input ampli?r or sawf, in which case external loads to vcc will be required, an example load for 44 mhz application, with a gain of 16 db is contained in ?ure (5). the typical if output impedance as upconverter and downconverter are contained in ?ures (17) and (18) respectively. in all applications care should be taken to achieve symmetric balance to the if outputs to maximise intermodulation performance. the typical key performance data at 5v vcc and 25 deg c ambient are shown in the section headed 'quick reference data'. pll frequency synthesiser the pll frequency synthesiser section contains all the elements necessary, with the exception of a reference frequency source and loop ?ter to control the oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. the lo signal from the oscillator drives an internal preampli?r, which provides gain and reverse isolation from the divider signals. the output of the preampli?r interfaces direct with the 15-bit fully programmable divider. the programmable divider is of mn+a architecture, where the dual modulus prescaler is 16/17, the a counter is 4-bits, and the m counter is 11 bits. the output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in
datasheet SL2100 4 ?ure (19). the typical application for the crystal oscillator is contained in ?ure (20) the output of the phase detector feeds a charge pump and loop ampli?r, which when used with an external loop ?ter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. the programmable divider output fpd divided by two and the reference divider output fcomp can be switched to port p0 by programming the device into test mode. the test modes are described in ?ure (21). the crystal reference frequency can be switched to bufref output by bit re as described in ?ure (22) programming the SL2100 is controlled by an i 2 c data bus and is compatible with both standard and fast mode formats. data and clock are fed in on the sda and scl lines respectively as de?ed by i 2 c bus format. the device can either accept data (write mode), or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. tables 1 and 2 in ?ure (23) illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one device in an i 2 c bus system. figure (23), table 3 shows how the address is selected by applying a voltage to the 'add' input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. write mode with reference to ?ure (23), table 1, bytes 2 and 3 contain frequency information bits 2 14 -2 0 inclusive. byte 4 controls the synthesiser reference divider ratio, see ?ure (19) and the charge pump setting, see ?ure (24). byte 5 controls the test modes, see ?ure (21), the buffered crystal reference output select re, see ?ure (22) and the output port p0. after reception and acknowledgement of a correct address (byte 1), the ?st bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. this procedure continues until a stop condition is received. the stop condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. to facilitate smooth ?e tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. read mode when the device is in read mode, the status byte read from the device takes the form shown in ?ure (23) table 2.
SL2100 datasheet 5 bit 1 (por) is the power-on reset indicator, and this is set to a logic '1' if the vcc supply to the device has dropped below 3v (at 25?c), e.g. when the device is initially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. bit 2 (fl) indicates whether the synthesiser is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. programmable features synthesiser programmable divider function as described above reference programmable divider function as described above. charge pump current the charge pump current can be programmed by bits c1 & c0 within data byte 4, as de?ed in ?ure (24). test mode the test modes are de?ed by bits t2 - t0 as described in ?ure (21) general purpose ports, p0 the general purpose port can be programmed by bits p0; logic '1' = on logic '0' = off (high impedance) buffered crystal reference output select the buffered crystal reference frequency can be selected by bit re as described in ?ure (22) 15 bit programmable divider i 2 c bus interface charge pump reference divider tank tankb sda scl add xtal xtalcap bufref port p0 drive pump ifoutput fpd/2 fcomp fpd ref osc osc rf input rf inputb ifoutputb figure 2 - SL2100 block diagram
datasheet SL2100 6 figure 4 - nominal output load as downconverter, 44mhz if output 15 pf 15 pf 10 uh 820 nh 820 nh 10 nf 15 14 SL2100 vcc 15 14 10 nh 10 nh vcc SL2100 output 33 ? sawf b1603 outputb 33 ? 200 ? 200 ? 100nf figure 3 - nominal output load as upconverter into differential sawf figure 5 - output load as downconverter to a differential ampli?r output 15 14 SL2100 10 nf 10 nf outputb vcc 680 nh 680 nh 100 nf
SL2100 datasheet 7 ch1 s 11 1 u fs start 50.000 000 mhz stop 950.000 000 mhz SL2100 rf i/p device 1 cor avg 50 prm 21 feb 2000 12:37:59 1 2 3 4 1_: 677.38 -502.03 6.3404 pf 50.000 000 mhz 2_: 56.961 -200.02 350 mhz 3_: 22.105 -106.34 650 mhz 4_: 9.5117 -66.727 949.91 mhz figure 6 - typical rf input impedance as broadband upconverter 100nf 200 ? 47nh rf input 10 9 100nf figure 7 - rf input impedance matching network as 50 -860mhz upconverter
datasheet SL2100 8 figure 10 - two tone intermodulation test condition spectrum, input referred ch1 s 11 1 u fs start 950.000 000 mhz stop 1 450.000 000 mhz SL2100 ip impedance pin9 cor smo prm 1 mar 2000 10:48:23 1 2 3 4 1_: 14.17 -45.779 3.4766 pf 1 000.000 000 mhz 2_: 14.324 -34.904 1.1 ghz 3_: 14.807 -33.699 1.2 ghz 4_: 16.213 -24.929 1.3 ghz figure 8 - typical rf input impedance as narrow band downcoverter 10 rf input 10nf 2.7pf 3.9nh 9 figure 9 - rf input impedance matching network as 1.22ghz downconverter 48 dbuv 94 dbuv iim3 -46dbc f2-f1 f1-df f2+df f1 f2 df 47 dbuv iim2; -47dbc
SL2100 datasheet 9 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 900 noise figure(in db) measured with 50 ? load input frequency (in mhz) figure 11 - input nf figure 12 - conversion gain as upconverter 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 900 input frequency (in mhz) terminated conversion gain (in db) measured with 50 ? load
datasheet SL2100 10 1 k ? varactor line bb555 2 pf figure 13 - upconverter oscillator application 70 75 80 85 90 95 0 100 200 300 400 500 600 700 800 900 input frequency phase noise measured with 50 ? load figure 14 - oscillator typical phase noise performance 20 21 1 k ? varactor line bb555 4.3 nh 2.5pf figure 15 - downconverter oscillator application
SL2100 datasheet 11 80 82 84 86 88 90 92 94 96 98 100 1040 1060 1080 1100 1120 1140 1160 1180 1200 lo frequency phase noise (at 10 khz offset) measured with 50 ? load 1220 figure 16 - typical phase noise performance as downconverter figure 17 - typical if output impedance as upconverter, single-ended figure 18 - typical if output impedance as downconverter, single-ended ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 400.000 000 mh z b1 cor avg 3 sm o prm 19 jan 2001 11:04:45 1 2 3 4 4_: 8.7988 -35.773 3.1778 pf 1 400.000 000 mhz 1_: 5.0039 -66.137 1 ghz 2_: 6.373 -51.047 1.15 ghz 3_: 9.3398 -44.512 1.25 ghz ch1 s 11 1 u fs start 10.000 000 mhz stop 100.000 000 mhz b2 pin14 5v cor avg 2 smo prm 23 jan 2001 14:03:25 1 2 3 4 4_: 283.34 -868.59 1.8323 pf 100.000 000 mhz 1_: 2.5804 k -994.38 10 mhz 2_: 1.1366 k -1.3737 k 40 mhz 3_: 488.88 -1.0823 k 70 mhz
datasheet SL2100 12 r4 r3 r2 r1 r0 ratio 00000 2 00001 4 00010 8 00011 16 00100 32 00101 64 00110 128 00111 256 01000 illegal state 01001 5 01010 10 01011 20 01100 40 01101 80 01110 160 01111 320 10000 illegal state 10001 6 10010 12 10011 24 10100 48 10101 96 10110 192 10111 384 11000 illegal state 11001 7 11010 14 11011 28 11100 56 11101 112 11110 224 11111 448 figure 19 - reference division ratios
SL2100 datasheet 13 xtalcap xtal 47pf 47pf 4mhz 47pf 4mhz xtalcap xtal SL2100 (down) xtalcap xtal SL2100 (up) 10nf 10k ? nc 10pf 47pf figure 20 - crystal oscillator application (typical) figure 21 - crystal oscillator application in dual conversion architecture
datasheet SL2100 14 * clocks need to be present on crystal and lo inputs to enable charge pump test modes and to toggle status byte bit fl t2 t1 t0 test mode description 0 0 0 normal operation 0 0 1 charge pump sink * status byte fl set to logic '0' 0 1 0 charge pump source * status byte fl set to logic '0' 0 1 1 charge pump disabled * status byte fl set to logic '1' 1 0 0 normal operation and port p0 = fpd/2 1 0 1 charge pump sink * status byte fl set to logic '0' port p0 = fcomp 1 1 0 charge pump source * status byte fl set to logic '0' port p0 = fcomp 1 1 1 charge pump disabled * status byte fl set to logic '1' port p0 = fcomp figure 21 - test modes re bufref output 0 disabled, high impedance 1 enabled figure 22 - buffered crystal reference output select
SL2100 datasheet 15 # programmed by connecting a 30 k ? resistor between pin and vcc msb lsb address 11000ma1ma00a byte 1 programmable divider 02 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 c1c0r4r3r2r1r0 a byte 4 control data t2 t1 t0 x x x re p0 a byte 5 table 1 - write data format (msb is transmitted rst) msb lsb address 11000ma1ma01a byte 1 programmable divider porfl000000a byte 2 table 2 - read data format (msb is transmitted rst) a : acknowledge bit ma1,ma0 : variable address bits (see table 3) 2 14 -2 0 : programmable division ratio control bits c1-c0 : charge pump current select (see ?ure (24)) r4-r0 : reference division ratio select (see ?ure (19)) t2-t0 : test mode control bits (see ?ure (21)) p0 : p0 port output state por : power on reset indicator fl : phase lock ?g x : 'don't care' ma1 ma0 address input voltage level 0 0 0-0.1vcc 0 1 open circuit 1 0 0.4vcc - 0.6 vcc # 1 1 0.9 vcc - vcc table 3 - address selection figure 23 - data formats
datasheet SL2100 16 c1 c0 current in a min typ max 0 0 +-98 +-130 +-162 0 1 +-210 +-280 +-350 1 0 +-450 +-600 +-750 1 1 +-975 +-1300 +-1625 figure 24 - charge pump current
SL2100 datasheet 17 electrical characteristics test conditions (unless otherwise stated) tamb = -40? to 85?c, vee= 0v, vcc=5v+-5% these characteristics are guaranteed by either production test or design. they apply within the speci?d ambient temperature and supply voltage unless otherwise stated. characteristic pin min typ max units conditions supply current 90 120 ma if outputs will be connected to vcc through the differential load as in ?ures (3)&(4) input frequency range 50 1400 mhz operating condition only output frequency range 30 1400 mhz operating condition only composite peak input signal 97 dbuv operating condition only all synthesiser related spurs on if output -60 dbc within channel bandwidth of 8 mhz and with input power of 60 dbuv upconverter application input frequency range 50 860 mhz input impedance 75 ? see ?ure (6), input return loss 6 db with input matching network as in ?ure (7) input noise figure 9.5 db see ?ure (11), with input matching network as in ?ure (7) conversion gain 9 db differential voltage gain to 200 ? load on output of sawf as in ?ure (3), see ?ure (12) gain variation across operation range -1 +1 db 50-860 mhz gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range through gain -20 db 45-1400 mhz cso -62 dbc measured with 128 channels at 62 dbuv ctb -64 dbc measured with 128 channels at 62 dbuv ipip2 2t 137 dbuv see note (2) ipip3 2t 116 dbuv see note (2)
datasheet SL2100 18 ipim2 2t -47 dbc see note (2), see ?ure (10) ipim3 2t -46 dbc see note (2), see ?ure (10) lo operating range 1 2.3 ghz maximum tuning range 0.9 ghz determined by application lo phase noise, ssb application as in ?ure (13), see ?ure (14) @ 10 khz offset -90 -85 dbc/hz @ 100 khz offset -110 -106 dbc/hz lo phase noise ?or -136 dbc/hz application as in ?ure (13) if output frequency range 1 1.4 ghz lo and harmonic leakage to rf input to device input fundamental 64 dbuv 2nd harmonic 81 dbuv 3rd harmonic 49 dbuv if output impedance see ?ure (17) downconverter application input frequency range 1000 1400 mhz input impedance 75 ? see ?ure (8) input return loss 12 db with input matching network as in ?ure (9) input noise figure 14 db tamb=27?c, with input matching network as in ?ure (9) conversion gain 12 db differential voltage gain to 50 ? load on output of impedance transformer as in ?ure (5) gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range through gain -20 db 45-1400 mhz ipip3 2t 117 dbuv see note (2) ipim3 2t -46 dbc see note (2), see ?ure (10) lo operating range 1 2.3 ghz maximum tuning range determined by application, see note (4) characteristic pin min typ max units conditions
SL2100 datasheet 19 lo phase noise, ssb see ?ure (16) @ 10 khz offset -94 -92 dbc/hz application as in ?ure (15) @ 100 khz offset -116 -112 dbc/hz lo phase noise ?or -136 dbc/hz application as in ?ure (13) if output frequency range 100 mhz if output impedance see ?ure (18) synthesiser sda, scl i 2 c 'fast mode' compliant input high voltage 3 5.5 v input low voltage 0 1.5 v input high current 10 ua input voltage = vcc input low current -10 ua input voltage = vee leakage current 10 ua vcc=vee hysterysis 0.8 v sda output voltage 0.4 v isink = 3 ma 0.6 v isink = 6 ma scl clock rate 400 khz charge pump output current see ?ure (24), vpin = 2v charge pump output leakage +-3 +-10 na vpin = 2v charge pump drive output current 0.5 ma vpin = 0.7v crystal frequency 2 20 mhz see ?ure (20) for application recommended crystal series resistance 10 200 ? 4 mhz parallel resonant crystal oscillator temperature stability tbc ppm/?c oscillator supply voltage stability tbc ppm/v characteristic pin min typ max units conditions
datasheet SL2100 20 notes (1) all power levels are referred to 75 ? and 0 dbm = 109 dbuv (2) any two tones within rf operating range at 94 dbuv beating within band, with output load as in ?ure (3) (3) port powers up in high impedance state (4) to maximise phase noise the tuning range should be minimised and q of resonator maximised. the application as in ?ure (15) has a tuning range of 200 mhz. external reference input frequency 2 20 mhz sinewave coupled through10 nf blocking capacitor external reference drive level 0.2 0.5 vpp sinewave coupled through 10 nf blocking capacitor phase detector comparison frequency 4 mhz equivalent phase noise at phase detector -152 dbc/hz ssb, within loop bandwidth 2 mhz -158 dbc/hz 250 khz local oscillator programmable divider division ratio 240 32767 reference division ratio see ?ure (19) output port see note (3) sink current 2 ma vport = 0.7 leakage current 10 ua vport =vcc buffered ref/comp output ac coupled 0.0625-20 mhz, output amplitude 0.35 vpp enabled by bit re=1 and default state on power-up output impedance 250 ? address select see ?ure (23) table (3) input high current 1 ma vin=vcc input low current -0.5 ma vin=vee characteristic pin min typ max units conditions
SL2100 datasheet 21 rf rfb 9 10 500k 500k v ref lo lob 20 21 if output if outputb 15 14 oscillator inputs rf inputs if outputs reference oscillator xtal v cc xtalcap 2 1 200 a sda/scl (pins 3 and 4) scl/sda 500k * on sda only v cc ack * output port p0 26
datasheet SL2100 22 loop ampli er 27 v cc 220 drive pump 28 add input v cc 120k 40k add 24 bufref ouput enable/ disable bufref v cc 5 1ma
SL2100 datasheet 23 absolute maximum ratings all voltages are referred to vee at 0v characteristic min max units conditions supply voltage -0.3 7 v rf input voltage 117 dbuv differential, ac coupled inputs all i/o port dc offsets -0.3 vcc+0.3 v sda, scl dc offsets -0.3 6 v vcc = vee to 5.25v storage temperature -55 150 ?c junction temperature 150 ?c package thermal resistance, chip to case 20 ?c/w package thermal resistance, chip to ambient 85 ?c/w power consumption at 5.25v 630 mw esd protection 2 kv mil-std 883b method 3015 cat1

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